搜索资源列表
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
fadder8
- 基于VHDL语言，编写一个32位全加器文件，可直接编译-Based on VHDL language, write a 32-bit full adder files can be directly compile
Ms32pci
- PCI-ip硬件描述语言-开源的，可以做参考设计，如果需要的话，-This models are written in VHDL! Author is Ovidiu Lupas! MASTER model generates PCI compliant signals checks Target signal compliance with PCI checks data received from Target for correctness generates
BARREL_SHIFTER
- IMPLEMENTATION OF 32 BIT BARREL SHIFTER IN VHDL
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
grlib-netlists-1.1.0.tar
- leon for 3 fpu. The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
parity_chk_32
- 这是一个32位的奇偶校验程序,VHDL代码,可用于FPGA.-32 bit parity check
parity_chk_32-
- 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
ARM32registergroup
- VHDL ARM 32位寄存器组的设计，基于Quartus II平台-VHDL ARM 32-bit register set design, based on the platform of Quartus II
Taddd_32_bbcdh
- 此程序源码使用VHDL语言，完成在32位十六进制加法器的基础上将输出出进行BCD码转换，实现输出是BCD码的32位二进制加法 可直接使用。 -This program source code using VHDL language, completed on the basis of 32-bit hexadecimal adder output BCD code conversion, the output is a 32-bit binary adder BCD code can be
clock
- 用vhdl写的数字电子时钟，能够定闹钟，定点报时，调时，用Quartus II 7.2 (32-Bit)写的，压缩文件，里面有源程序，仿真文件等（就是所建的工程）-Digital electronic clock vhdl write, to set the alarm clock, designated chime tune, written using Quartus II 7.2 (32-Bit), compressed files, source code and simulation
ads1282_code
- 用VHDL写的控制TI公司32位高精度ADC的程序，可以可靠运行，已经应用于实际项目-Control TI' s 32-bit precision ADC program written using VHDL, reliable operation, has been applied to the actual project
32counter
- 用VHDL语言设计一个32位二进制计数器并进行功能仿真 2.用VHDL语言设计一个8位数码扫描显示电路 -A 32-bit binary counter design using VHDL language and functional simulation using VHDL language design an 8-bit digital scanning display circuit
2dpsk4
- vhdl实现2dpsk，软件是Quartus II 9.0 (32-Bit)-2dpsk VHDL
encrypt_8_tea_complete
- This complete project for 8-bit TEA algorithm. Actually, at least 32-bit for TEA and you can change number of bits. This folder consists of five vhdl files. one top level entity named encrypt_8 and the remaining four are low level entities.-This is c
my_32fp_mult
- 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
filter_VHDL
- FIR filter design using VHDL for 32 bit signed coefficientand 32 bit input and decimation is 4 and its working good
ALU32
- 32 bit ALU RTL Code using VHDL
generateur_rossel
- this is vhdl program of rosseler chaotic generator 32 bit fixed point.
adder32bit
- vhdl code for 32 bit binary addition